PCI (Peripheral Component Interconnect) Express is a serialized I/O interconnect standard developed to meet the increasing bandwidth needs of the next generation of computer systems. PCI Express was designed to be fully compatible with the widely used PCI local bus standard. PCI is beginning to hit the limits of its capabilities, and while extensions to the PCI standard have been developed to support higher bandwidths and faster clock speeds, these extensions may be insufficient to meet the rapidly increasing bandwidth demands of PCs in the near future. With its high-speed and scalable serial architecture, PCI Express may be an attractive option for use with, or as a possible replacement for, PCI in computer systems. [The PCI Express architecture is described in the PCI Express Base Architecture Specification, Revision 1.0 (Initial release Jul. 22, 2002), which is available through the PCI-SIG (PCI-Special Interest Group) (http://www.pcisig.com)].
AS is an extension to the PCI Express architecture. AS utilizes a packet-based transaction layer protocol that operates over the PCI Express physical and data link layers. The AS architecture provides a number of features common to multi-host, peer-to-peer communication devices such as blade servers, clusters, storage arrays, telecom routers, and switches. These features include support for flexible topologies, packet routing, congestion management (e.g., credit-based flow control), fabric redundancy, and fail-over mechanisms. The AS architecture is described in the Advanced Switching Core Architecture Specification, Revision 1.0 (December 2003), which is available through the ASI-SIG (Advanced Switching Interconnect-SIG) (http//:www.asisig.org).
Like reference numerals in different figures indicate like elements.